1. Field of the Invention
This invention relates to multiprocessor systems, and more particularly to the transmission of critical data between processors.
2. Description of the Related Art
Modern computer systems typically implement a memory hierarchy in which a processor maintains frequently accessed data in one or more onboard caches. In general, this stored data is a duplicate of data stored elsewhere in a system memory. When a processor needs data, the processor typically fetches the desired data from memory (such as, for example, a memory in the random access memory (RAM) family) and loads it into the cache for future use. In some systems, this fetched data may include only the desired data (i.e., critical data), while in other systems the fetched data may include an entire cache line containing both critical data and other non-critical data.
Some computer systems are now using multiple processors either located on a single die, or module, or coupled together via a bus. Frequently, these processors share memory that contains data that is accessible by each of the processors. For example, a pair of processors may each be coupled to a common memory, or may each be coupled to separate, accessible memories. In either situation, the processors may share the stored data. Accordingly, various techniques have been implemented to maintain coherency between the shared memory and the onboard caches located on each of the processors. In some conventional systems, the latency associated with receiving the critical data can be problematic.